Pattern sheet, semiconductor intermediate product, and hole etching method

US12106970B2 · kind B2 · utility

Assignee

• BEIJING NAURA MICROELECTRONICS EQUIPMENT CO., LTD. · CN

Inventors

• Qiushi Xie · Beijing, CN
• Xiaoping Shi · Lo Wu, CN
• Qingjun Zhou · Sunnyvale, US
• Dongsan Li · Beijing, CN
• Chun Wang · Beijing, CN
• Yiming Zhang · Beijing, CN

Key dates

• Filing date: Apr 2, 2021
• Grant date: Oct 1, 2024
• Expiry date: Apr 2, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L23/481
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The present disclosure discloses a pattern sheet, a semiconductor intermediate product, and a hole etching method. The pattern sheet includes a substrate, a dielectric layer, and a mask structure. The mask structure includes a multi-layer mask layer. An uppermost mask layer is a photoresist layer. A thickness of each layer of the mask layer and etching selectivity ratios between the layers below the mask layer satisfy that in each two neighboring layers of the mask layer, a lower layer of the mask layer is etched to form a through-hole penetrating a thickness of the lower layer of the mask layer, a remaining thickness of the upper layer of the mask layer is greater than or equal to zero.