Display backplane including an array of tiles
US12107072B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2021 |
| Grant date | Oct 1, 2024 |
| Priority date | — |
| Expiry date | Dec 12, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/857
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A backplane for controlling a display is disclosed. The backplane includes a plurality of tiles formed into an array. Each of the plurality of tiles includes a plurality of complementary metal-oxide-semiconductor backplane dies. Edges of the backplane dies that form a perimeter of the array include electrical connections that direct electrical signals to at least one of the CMOS backplane dies. A display assembly is also disclosed wherein the display assembly includes a backplane having an array of tiles. Each tile includes a plurality of electrically coupled CMOS backplane dies, where edges of the tiles that form an outer perimeter of the array include electrical connections directing electrical signals to one or more of the plurality of CMOS backplane dies. The display assembly further includes at least one light emitting diode array electrically coupled with at least one tile.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.