Integrated circuit devices
US12107122B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2023 |
| Grant date | Oct 1, 2024 |
| Priority date | — |
| Expiry date | Apr 26, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
An integrated circuit device includes: a fin-type active region on a substrate and including a fin top surface at a first level; a gate line on the fin-type active region; and an insulating structure on a sidewall of the fin-type active region. The insulating structure includes: a first insulating liner in contact with a sidewall of the fin-type active region; a second insulating liner on the first insulating liner and including an uppermost portion at a second level c than the first level; a lower buried insulating layer facing the sidewall of the fin-type active region and including a first top surface facing the gate line at a third level lower than the second level; and an upper buried insulating layer between the lower buried insulating layer and the gate line and including a second top surface at a fourth level equal to or higher than the second level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.