High-threshold power semiconductor device and manufacturing method thereof
US12107167B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 20, 2021 |
| Grant date | Oct 1, 2024 |
| Priority date | — |
| Expiry date | Mar 12, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
Abstract
The present invention discloses a high-threshold power semiconductor device and a manufacturing method thereof. The high-threshold power semiconductor device includes, in sequence from bottom to top: a metal drain electrode, a substrate, a buffer layer, and a drift region; further including: a composite column body which is jointly formed by a drift region protrusion, a columnar p-region and a columnar n-region on the drift region, a channel layer, a passivation layer, a dielectric layer, a heavily doped semiconductor layer, a metal gate electrode and a source metal electrode. The composite column body is formed by sequentially depositing a p-type semiconductor layer and an n-type semiconductor layer on the drift region and then etching same. The channel layer and the passivation layer are formed in sequence by deposition. Thus, the above devices are divided into a cell region and a terminal region. The dielectric layer, the heavily doped semiconductor layer, the metal gate electrode and the source metal electrode only exist in the cell region, and the passivation layer of the terminal region extends upwards and is wrapped outside the channel layer. This structure can increase a th…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.