Display panel interconnection line configurations
US12108641B2 · kind B2 · utility
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2References
20Claims
0Family size
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Key dates
| Filing date | Oct 13, 2021 |
| Grant date | Oct 1, 2024 |
| Priority date | — |
| Expiry date | Jan 12, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K2102/341
Abstract
A display panel includes a substrate. The substrate includes a display area, a bonding area disposed on one side of the display area and a fan-out area disposed between the bonding area and the display area. The fan-out area includes at least two metal layers, a first planarization layer and a first interconnection line layer which are stacked on a surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.