Semiconductor structure, memory cell and memory array
US12108682B2 · kind B2 · utility
0Cited by
8References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2021 |
| Grant date | Oct 1, 2024 |
| Priority date | — |
| Expiry date | Dec 5, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a semiconductor structure, a memory cell and a memory array. An nT-MRAM can be realized by a relatively simple structure. Transistors connected to multiple MTJs are connected by connecting pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.