Dynamic inclusive last level cache
US12111762B2 · kind B2 · utility
0Cited by
2References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2020 |
| Grant date | Oct 8, 2024 |
| Priority date | — |
| Expiry date | Oct 5, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1044
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment of an integrated circuit may comprise a core, and a cache controller coupled to the core, the cache controller including circuitry to identify data from a working set for dynamic inclusion in a next level cache based on an amount of re-use of the next level cache, send a shared copy of the identified data to a requesting core of one or more processor cores, and maintain a copy of the identified data in the next level cache. Other embodiments are disclosed and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.