Memory hub providing cache coherency protocol system method for multiple processor sockets comprising multiple XPUs
US12111775B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2021 |
| Grant date | Oct 8, 2024 |
| Priority date | — |
| Expiry date | Dec 17, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Examples described herein relate to an apparatus that includes at least two processing units and a memory hub coupled to the at least two processing units. In some examples, the memory hub includes a home agent. In some examples, the memory hub is to perform a memory access request involving a memory device, a first processing unit among the at least two processing units is to send the memory access request to the memory hub. In some examples, the first processing unit is to offload at least some but not all home agent operations to the home agent of the memory hub. In some examples, the first processing unit comprises a second home agent and wherein the second home agent is to perform the at least some but not all home agent operations before the offload of at least some but not all home agent operations to the home agent of the memory hub. In some examples, based on provision of the at least some but not all home agent operations to be performed by the second home agent, the second home agent is to perform the at least some but not all home agent operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.