Method for analyzing static analog integrated circuit layout
US12112111B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | May 15, 2024 |
| Grant date | Oct 8, 2024 |
| Priority date | — |
| Expiry date | May 15, 2044 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02E60/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a method for analyzing a static analog integrated circuit layout, corresponding simulation netlists are generated from an integrated circuit layout by parasitic parameter extraction, and device-node hypergraph or graph structures reflecting a circuit topological structure are generated from the simulation netlists. Then, characteristics of RC local networks between ports of individual device groups to be matched are analyzed. An independent source current is provided at i-ports of the RC networks, AC analysis is performed on the RC local networks to acquire impedance values of j-ports at different frequencies, and then a circuit mismatch condition is determined by comparing the impedance values of the individual RC local networks. The method automatically analyzes the analog integrated circuit layout to allow automatic analysis and determination of characteristic differences between a layout and a schematic design, improving the reliability of circuit mismatch examination and the efficiency of layout design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.