Complementary die-to-die interface
US12112113B2 · kind B2 · utility
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18References
20Claims
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Key dates
| Filing date | Mar 5, 2021 |
| Grant date | Oct 8, 2024 |
| Priority date | — |
| Expiry date | Apr 22, 2043 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a first instance and a second instance of an integrated circuit. The integrated circuits include respective external interfaces with a physical pin layout having transmit and receive pins for a particular bus located in complementary positions relative to an axis of symmetry. The external interfaces of the first and second instances of the integrated circuit are positioned such that the transmit and receive pins for the given I/O signal on the first instance are aligned, respectively, with the receive and transmit pins for the given I/O signal on the second instance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.