Loop support extensions
US12112171B2 · kind B2 · utility
0Cited by
6References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 26, 2020 |
| Grant date | Oct 8, 2024 |
| Priority date | — |
| Expiry date | Dec 19, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4881
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for processing loops are described. An exemplary apparatus at least includes decoder circuitry to decode a single instruction, the single instruction to include a field for an opcode, the opcode to indicate execution circuitry is to perform an operation to configure execution of one or more loops, wherein the one or more loops are to include a plurality of configuration instructions and instructions that are to use metadata generated by ones of the plurality of configuration instructions; and execution circuitry to perform the operation as indicated by the opcode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.