Real-time scheduling for a heterogeneous multi-core system
US12112196B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2021 |
| Grant date | Oct 8, 2024 |
| Priority date | — |
| Expiry date | May 29, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7807
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A heterogeneous multi-core system that executes a real-time system for an automobile includes a plurality of system-on chips in electronic communication with one another. Each system-on-chip includes a plurality of central processing units (CPUs) arranged into a plurality of logical domains. The heterogeneous multi-core system also includes a plurality of scheduled tasks that are executed based on an execution pipeline and each execute a specific set of tasks for one of the logical domains. The plurality of scheduled tasks includes at least one offset scheduled task that is executed at an offset time and a reference scheduled task located at an execution stage upstream in the execution pipeline relative to the offset scheduled task. The reference scheduled task communicates data to the offset scheduled task and the offset time represents a period of time measured relative to the reference scheduled task.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.