Processor with hardware pipeline
US12112197B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2022 |
| Grant date | Oct 8, 2024 |
| Priority date | — |
| Expiry date | Oct 11, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4843
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor has a register bank to which software writes descriptors specifying tasks to be processed by a hardware pipeline. The register bank includes a plurality of register sets, each for holding the descriptor of a task. The processor includes a first selector operable to connect the execution logic to a selected one of the register sets and thereby enable the software to write successive ones of said descriptors to different ones of said register sets. The processor also includes a second selector operable to connect the hardware pipeline to a selected one of the register sets. The processor further comprises control circuitry configured to control the hardware pipeline to begin processing a current task based on the descriptor in a current one of the register sets while the software is writing the descriptor of another task to another of the register sets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.