Lossless tiling in convolution networks—resetting overlap factor to zero at section boundaries

US12112250B2 · kind B2 · utility

Assignee

• SambaNova Systems, Inc. · US

Inventors

• Tejas Nagendra Babu Nama · Sunnyvale, US
• Ruddhi Chaphekar · Santa Clara, US
• Ram Sivaramakrishnan · San Jose, US
• Raghu Prabhakar · San Jose, US
• Sumti Jairath · Santa Clara, US
• Junjue Wang · San Mateo, US
• Kaizhao Liang · Palo Alto, US
• Adi Fuchs · Princeton Colonial Park, US
• Matheen Musaddiq · Austin, US
• Arvind Krishna Sujeeth · San Francisco, US

Key dates

• Filing date: Apr 4, 2022
• Grant date: Oct 8, 2024
• Expiry date: Dec 10, 2042

Classification

• Technology area (CPC G): Physics
• CPC primary: G06N3/082
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A data processing system includes compile time logic to section a graph into a sequence of sections, including a first section followed by a second section. The compile time logic configured the first section to generate a first output in a first non-overlapping target configuration in response to processing an input in a first overlapping input configuration, and configures the second section to generate a second output in a second non-overlapping target configuration in response to processing the first output in a second overlapping input configuration. The compile time logic also creates a set of computer instructions to execute the first section and the second section on a target processing system.