Sense amplifier circuit and data read method
US12112824B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2023 |
| Grant date | Oct 8, 2024 |
| Priority date | — |
| Expiry date | Jun 25, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4094
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments relate to a sense amplifier circuit and a data read method. The sense amplifier circuit includes: a first P-type transistor connected to a first signal terminal; a second P-type transistor connected to a second signal terminal; a first N-type transistor connected to a third signal terminal; a second N-type transistor connected to a fourth signal terminal; a first offset cancellation subcircuit configured to connect a first read bit line to a second complementary read bit line in response to a first offset cancellation signal; a second offset cancellation subcircuit configured to connect a first complementary read bit line to a second read bit line in response to a second offset cancellation signal; a first write-back subcircuit configured to connect the first complementary read bit line to the second complementary read bit line in response to a first write-back signal; and a second write-back subcircuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.