Memory array circuits, memory structures, and methods for fabricating a memory array circuit
US12112829B2 · kind B2 · utility
0Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2022 |
| Grant date | Oct 8, 2024 |
| Priority date | — |
| Expiry date | Jan 13, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array circuit includes a memory array and a set of dummy cells surrounding the memory array. The first memory array includes a first set of memory cells located in an inner area of the memory array and a second set of memory cells located along an edge of the memory array. Each dummy cell includes one or more active regions and multiple gate structures over the one or more active regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.