System on wafer assembly structure and assembly method thereof
US12112991B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2023 |
| Grant date | Oct 8, 2024 |
| Priority date | — |
| Expiry date | Oct 30, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/54426
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A system on wafer assembly structure and an assembly method thereof. The system on wafer assembly structure comprises: a wafer layer, a dielectric layer and a circuit board layer sequentially stacked, and each provided with a bonding region, a testing region and an alignment region, respectively, a first assembly, and a second assembly, wherein the first assembly is arranged on one side of the wafer layer far away from the dielectric layer, and comprises a bearing portion and at least one latch portion connected with each other, and the bearing portion is detachably connected with the wafer layer. The second assembly is at least partially arranged around the first assembly. The second assembly has a hole portion for accommodating a latch portion, and the inner diameter of the hole portion is larger than the outer diameter of the latch portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.