Microelectronic circuit capable of selectively activating processing paths, and a method for activating processing paths in a microelectronic circuit

US12113530B2 · kind B2 · utility

Assignee

• MINIMA PROCESSOR OY · FI

Inventor

• Navneet Gupta · Ghaziabad, IN

Key dates

• Filing date: Dec 5, 2018
• Grant date: Oct 8, 2024
• Expiry date: Aug 12, 2040

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02D10/00
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A microelectronic circuit comprises a plurality of logic units and register circuits arranged into a plurality of processing paths. At least one monitor circuit (404) is associated with a first register circuit (301), said monitor circuit (404) being configured to produce a timing event observation signal as a response to a change in a digital value at an input (D) of the first register circuit (301) that took place later than an allowable time limit defined by a triggering signal (CP) to said first register circuit (301). A first processing path goes through a first logic unit (501) to said first register circuit (301) and is a delay critical processing path due to an amount of delay that it is likely to generate. The microelectronic circuit comprises a controllable data event injection point (503) for controllably generating a change of a digital value propagating to said first logic unit (501) irrespective of what other data is processed on said first processing path. Said microelectronic circuit is configured to freeze a first digital value stored in said first register circuit (301) for a time during which the change generated through said controllable data event injection poi…