Pipeline clock driving circuit, computing chip, hashboard, and computing device
US12113537B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2024 |
| Grant date | Oct 8, 2024 |
| Priority date | — |
| Expiry date | Jan 12, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/15
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a pipeline clock driving circuit, a computing chip, a hashboard, and a computing device. Disclosed is a pipeline clock driving circuit, configured to provide a pulse clock signal to a pipeline, including: a plurality of stages of clock driving circuits, each stage being configured to provide the pulse clock signal to a corresponding operation stage of the pipeline; a clock source, coupled to an input of a first-stage clock driving circuit, each stage of the clock driving circuits including: a trigger, coupled to an input of a current-stage clock driving circuit; a delay module, including a first delay sub-module, the first delay sub-module delaying a pulse signal output by the trigger and feeding a delayed pulse signal back to the trigger as a feedback pulse signal; and a combinational logic module, performing a combinational logic operation on the pulse signal and the feedback pulse signal to generate the pulse clock signal to be provided to a corresponding operation stage, where the delay module further includes a second delay sub-module, and the second delay sub-module delays the pulse signal and outputs the delayed pulse signal to a next-stage …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.