Calibration detector with two offset compensation loops
US12113542B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 2022 |
| Grant date | Oct 8, 2024 |
| Priority date | — |
| Expiry date | Jan 20, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/785
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Described herein are related to a calibration circuit for a digital to analog converter (DAC) including a plurality of DAC cells. The calibration circuit including a chopper circuit configured to receive a first signal from a first DAC cell of the plurality of DAC cells and receive a second signal from a second DAC cell of the plurality of DAC cells. The calibration circuit including a comparator circuit configured to receive the first signal and the second signal from the chopper circuit, provide a third signal indicating at least one of the first signal or the second signal. The calibration circuit also including a second circuit configured to offset a first voltage associated with the comparator circuit and configured to offset a second voltage associated with the chopper circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.