Digital signal processing of randomly jittered under-sampled sequence
US12113553B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 3, 2022 |
| Grant date | Oct 8, 2024 |
| Priority date | — |
| Expiry date | Dec 28, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L9/0869
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods/systems employ randomly jittered under-sampling to reduce a sampling rate required to convert an analog signal to a digital signal in electronic devices and other applications that perform digital signal processing on the signal. The methods/systems can greatly reduce the nominal sampling rate for such applications where RMS, peak and mean estimates of the signal are desired for both the entire band-limited signal and separate estimates for each frequency component. This can in turn result in large cost savings, as less complex and thus less expensive controllers and related components may be used to perform the sampling. As well, the methods/systems herein can provide reasonably accurate waveform estimates that allow additional cost savings in bill of materials (BOM) and printed circuit board assembly (PCBA) footprint and real-estate by eliminating the need for certain analog components, such as signal conditioning components.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.