PUCCH format 1 signal processing with reduced complexity
US12113657B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2022 |
| Grant date | Oct 8, 2024 |
| Priority date | — |
| Expiry date | Nov 28, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L5/0051
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A network device includes receiver circuitry and a processor. The receiver circuitry is configured to receive a signal from a plurality of terminal devices, over a physical uplink control channel (PUCCH) format 1 (FMT1). The processor is coupled to the receiver circuitry, and is configured to perform processing on the received signal to obtain decoded data corresponding to the plurality of terminal devices, and utilize the decoded data for handling further communications with the plurality of terminal devices. In the processing, the processor is configured to obtain a demodulated signal sequence from the received signal. The processor is further configured to perform, on the demodulated signal sequence, a transform from a frequency domain into a time domain to obtain a time domain sequence. The processor is further configured to extract, from the time domain sequence, one or more data blocks corresponding to each terminal device among the plurality of terminal devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.