Pixel output parasitic capacitance reduction and predictive settling assist
US12114089B2 · kind B2 · utility
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38References
20Claims
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Key dates
| Filing date | Aug 19, 2022 |
| Grant date | Oct 8, 2024 |
| Priority date | — |
| Expiry date | Aug 26, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/811
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein are electronic devices and image sensors containing pixel arrays, layouts of electrical signal lines for such pixel arrays, and methods of pixel read out operations, including row read operations, for such pixel arrays. Layouts are disclosed that have reduced sets of shielding or ground lines. In some layouts, shielding ground lines are used only between pairs of adjacent pixel output signal lines (OSLs). Also disclosed is a method of using one OSL within a pair of adjacent pixel OSLs to provide settling assist of the pixel output signal on the other OSL of the adjacent pair of OSLs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.