Array substrate including connection layer and display panel having the same
US12114546B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 16, 2021 |
| Grant date | Oct 8, 2024 |
| Priority date | — |
| Expiry date | Jul 16, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K2102/351
Abstract
An array substrate and a display panel are provided. The array substrate includes a substrate, a planarization layer, a connection layer, and an anode layer. The planarization layer is disposed on a side of the substrate and is provided with a first via hole. The connection layer includes a connecting portion. The connecting portion is disposed in the first via hole and extends to a surface of the planarization layer. The anode layer is disposed on a surface of the connecting portion away from the planarization layer. In the array substrate, the connecting portion is disposed between the planarization layer and the anode layer, which can prevent pixels of the display panel from generating black dots.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.