Interface device and signal transceiving method thereof
US12117864B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 23, 2022 |
| Grant date | Oct 15, 2024 |
| Priority date | — |
| Expiry date | Feb 24, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00019
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interface device and a signal transceiving method thereof are provided. The interface device includes a master circuit and a slave circuit. The slave circuit includes a second receiver, a clock generator, a sampler, and a comparator. The first receiver and second receiver respectively receive input data and a clock signal from the master circuit. The clock generator delays the clock signal according to a delay value to generate a delayed clock signal, and generates a plurality of sampling signals according to the delayed clock signal. The sampler samples the input data according to the sampling signals to generate a plurality of sampling results. The comparator compares the sampling results to generate a comparison result. The clock generator adjusts the delay value according to the comparison result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.