SOC for operating plural NPUS according to plural clock signals having multi-phases
US12117866B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2023 |
| Grant date | Oct 15, 2024 |
| Priority date | — |
| Expiry date | Sep 25, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system-on-chip (SoC) may comprise a semi-conductor substrate; a first circuitry, disposed on the semi-conductor substrate, provided for a first neural processing unit (NPU) configured to perform operations of an artificial neural network model (ANN); a second circuitry, disposed on the semi-conductor substrate, provided for a second NPU configured to perform operations of an ANN model, each of the first NPU and the second NPU including a plurality of processing elements (PEs), the plurality of PEs including an adder, a multiplier, and an accumulator; and a clock signal supply circuit, disposed on the semi-conductor substrate, configured to output one or more clock signals, wherein a first clock signal among the one or more clock signals may be supplied to the first NPU, and a second clock signal among the one or more clock signals may be supplied to the second NPU.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.