Computer architecture with disaggregated memory and high-bandwidth communication interconnects

US12117930B2 · kind B2 · utility

Assignee

• Luminous Computing, Inc. · US

Inventors

• David Cureton Baker · Austin, US
• Ari Novack · New York, US
• Donovan Scott Popps · Austin, US
• Benjamin Wiley Melton · Charlottesville, US
• Bryan Cope · Austin, US
• Mark A. Baur · Austin, US
• Anahita Shayesteh · Los Altos, US

Key dates

• Filing date: Jan 13, 2023
• Grant date: Oct 15, 2024
• Expiry date: Mar 19, 2043

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2212/254
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Conventional high performance computer connections are electron-based systems, which require the memory packages to be as close as mechanically possible to the computation engine. Low power and high bandwidth communication, e.g. photonic, links can drastically change the architecture of high-performance computers by eliminating the bottlenecks in communication. A computer system comprises: a plurality of memory aggregation devices configured to retrieve data from and store data in a plurality of random access memory modules forming a unified contiguous memory address space disaggregated from a processing unit; a plurality of computational devices configured for simultaneously launching a plurality of data signals including memory read and/or write requests for the data to the plurality of memory aggregation devices; and a plurality of communication links coupling each of the plurality of memory aggregation devices to each of the plurality of computational devices for transferring the data therebetween.