Using physical address proxies to handle synonyms when writing store data to a virtually-indexed cache
US12117937B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2024 |
| Grant date | Oct 15, 2024 |
| Priority date | — |
| Expiry date | Jan 8, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6032
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor includes a virtually-indexed L1 data cache that has an allocation policy that permits multiple synonyms to be co-resident. Each L2 entry is uniquely identified by a set index and a way number. A store unit, during a store instruction execution, receives a store physical address proxy (PAP) for a store physical memory line address (PMLA) from an L1 entry hit upon by a store virtual address, and writes the store PAP to a store queue entry. The store PAP comprises the set index and the way number of an L2 entry that holds a line specified by the store PMLA. The store unit, during the store commit, reads the store PAP from the store queue, looks up the store PAP in the L1 to detect synonyms, writes the store data to one or more of the detected synonyms, and evicts the non-written detected synonyms.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.