Semiconductor memory devices and memory systems including the same
US12118221B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2023 |
| Grant date | Oct 15, 2024 |
| Priority date | — |
| Expiry date | Apr 20, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array, a row hammer management circuit and a refresh control circuit. The row hammer management circuit automatically stores random count data in count cells of each of a plurality of memory cell rows during a power-up sequence of the semiconductor memory device and determines counted values by counting a number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller and stores the counted values in the count cells of each of the plurality of memory cell rows as count data. The refresh control circuit receives a hammer address and performs a hammer refresh operation on one or more of the plurality of memory cell rows that are physically adjacent to a memory cell row that corresponds to the hammer address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.