Removal of hardware intellectual property and programmable replacement
US12118282B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 15, 2021 |
| Grant date | Oct 15, 2024 |
| Priority date | — |
| Expiry date | Mar 8, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In general, embodiments of the present disclosure provide methods, apparatus, systems, computer program products, computing devices, computing entities, and/or the like for altering a design of a hardware intellectual property (IP). In accordance with various embodiments, a representation of the design of the hardware IP is converted to generate a control and data flow graph (CDFG) for the design. An entropy analysis of the CDFG is conducted to identify one or more control paths and/or data paths for removal. Responsive to identifying control path(s) for removal, control logic for the control path(s) is removed from the design and replaced with first reconfigurable logic. Responsive to identifying data path(s) for removal, datapath logic for the data path(s) is removed from the design and replaced with second reconfigurable logic. Logic synthesis is then performed on the design, along with verification to check functional correctness of the design of the hardware.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.