Signal synchronization adjustment method and signal synchronization adjustment circuit
US12119041B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 6, 2023 |
| Grant date | Oct 15, 2024 |
| Priority date | — |
| Expiry date | Jul 8, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a signal synchronization adjustment method and a signal synchronization adjustment circuit, for applying to data reading according to a reference clock signal between a memory controller and a dynamic random access memory in an electronic device. First, the memory controller triggers a command signal to the dynamic random access memory; then, the dynamic random access memory delays for a column selection signal latency time according to a first rising edge of the reference clock signal, and then triggers a column selection signal; after that, the dynamic random access memory delays for an internal data strobe signal latency time, and then triggers an internal data strobe signal; finally, the dynamic random access memory delays for an external data strobe signal latency time, and then triggers an external data strobe signal. The signal synchronization adjustment circuit is applied to the signal synchronization adjustment method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.