Memory devices and methods for controlling row hammer
US12119044B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 4, 2022 |
| Grant date | Oct 15, 2024 |
| Priority date | — |
| Expiry date | Mar 8, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/408
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices and methods for controlling a row hammer are provided. The memory device includes a memory cell array including a word line and a plurality of counter memory cells storing an access count value of the word line, and a control logic circuit configured to monitor a row address accessing the word line during a row hammer monitoring time frame and to determine the row address to be a row hammer address when the number of times the word line is accessed is greater than or equal to a threshold value, wherein the row hammer address is to be stored in an address storage. The control logic circuit is further configured to hold up a determination operation for a next row hammer address, based on activation of a latch full signal indicating that there is no free space to store the row hammer address in the address storage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.