Readout circuit structure
US12119047B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2022 |
| Grant date | Oct 15, 2024 |
| Priority date | — |
| Expiry date | Jan 3, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A readout circuit structure is provided, which includes: a first sense amplification circuit and a second sense amplification circuit, disposed adjacent to each other along an extension direction of a bit line, here the first sense amplification circuit is coupled to one memory array in the adjacent memory arrays by a first bit line, and is coupled to the other memory array by a first complementary bit line, and the second sense amplification circuit is coupled to one memory array in the adjacent memory arrays by a second bit line, and is coupled to the other memory array by a second complementary bit line; a first equalization pipe, connected to the first bit line; a second equalization pipe, connected to the first complementary bit line; a third equalization pipe, connected to the second bit line; and a fourth equalization pipe, connected to the second complementary bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.