Flash memory device having multi-stack structure and channel separation method thereof
US12119066B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2022 |
| Grant date | Oct 15, 2024 |
| Priority date | — |
| Expiry date | Apr 22, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory device is provided. The flash memory device includes: a first memory cell; a second memory cell on the first memory cell; and a third memory cell between the first memory cell and the second memory cell. The first memory cell, the second memory cell and the third memory cell share a channel. The third memory cell is configured to block channel sharing between the first memory cell and the second memory cell based on a channel separation voltage provided in first to k-th program loops. The third memory cell is configured to connect the channel sharing between the first memory cell and the second memory cell based on a channel connection voltage provided to the third memory cell in a (k+1)-th program loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.