Circuit for receiving data, system for receiving data, and memory device
US12119077B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 23, 2022 |
| Grant date | Oct 15, 2024 |
| Priority date | — |
| Expiry date | Nov 30, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure provide a circuit for receiving data, a system for receiving data, and a memory device. The circuit for receiving data includes: a first amplification module, including: an amplification unit, provided with a first node, a second node, a third node, and a fourth node; a first N-channel metal oxide semiconductor (NMOS) transistor and a second NMOS transistor, the first NMOS transistor being provided with one terminal connected to the first node and another terminal connected to one terminal of the second NMOS transistor, another terminal of the second NMOS transistor being connected to the second node, a gate of one of the first NMOS transistor and the second NMOS transistor being configured to receive a first complementary feedback signal, and a gate of the other one of the first NMOS transistor and the second NMOS transistor being configured to receive an enable signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.