Data processing circuit and semiconductor memory divided into segments
US12119078B2 · kind B2 · utility
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18Claims
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Key dates
| Filing date | Jun 9, 2022 |
| Grant date | Oct 15, 2024 |
| Priority date | — |
| Expiry date | Dec 1, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing circuit includes a primary transmission path, multiple secondary transmission paths and multiple storage arrays which share the primary transmission path. Each storage array includes at least two sub-arrays, and the secondary transmission path is formed between each sub-array and the primary transmission path, and the sub-array transmits a signal through the secondary transmission path and the primary transmission path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.