Semiconductor integrated circuit device
US12119349B2 · kind B2 · utility
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5Claims
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Key dates
| Filing date | Aug 17, 2021 |
| Grant date | Oct 15, 2024 |
| Priority date | — |
| Expiry date | Apr 3, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/974
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A cell row includes an inverter cell having a logic function and a termination cell having no logic function. The termination cell is arranged at one of two ends of the cell row. A gate line and dummy gate lines are arranged in the same layer in a Z direction. Local interconnects are arranged in the same layer in the Z direction. Local interconnects are arranged in the same layer in the Z direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.