Semiconductor IC device including passivation layer for inactivating a dopant in a p-type semiconductor layer and method of manufacturing the same
US12119397B2 · kind B2 · utility
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13Claims
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Key dates
| Filing date | Sep 2, 2021 |
| Grant date | Oct 15, 2024 |
| Priority date | — |
| Expiry date | Nov 6, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/87
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit device includes: a channel layer, a barrier layer; a first p-type semiconductor layer and a second p-type semiconductor layer, spaced apart from each other on the barrier layer; and a passivation layer on the first p-type semiconductor layer and the second p-type semiconductor layer. The passivation layer may partially inactivate a dopant of at least one of the first p-type semiconductor layer and the second p-type semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.