Amplifier circuit and display apparatus having the same
US12119795B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2023 |
| Grant date | Oct 15, 2024 |
| Priority date | — |
| Expiry date | Nov 3, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/87
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is an amplifier circuit comprising a first stage having first and second input terminals, a second stage configured to amplify a voltage supplied from the first stage and including a pull-up node and a pull-down node, a third stage including an output terminal, a tenth PMOS transistor, and a tenth NMOS transistors having gate electrodes respectively connected to the pull-up node and the pull-down node of the second stage, the third stage configured to perform a pull-up driving and pull-down driving of the amplified voltage, a first boosting circuit including an eleventh PMOS transistor having a gate electrode connected to the pull-up node and the first boosting circuit configured to increase a current in the first stage, and a second boosting circuit including an eleventh NMOS transistor having a gate electrode connected to the pull-down node and configured to increase the current in the first stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.