Patent · US Active

Embedded pattern generator

US12119826B2 · kind B2 · utility

0Cited by
0References
21Claims
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Assignee

Inventors

Key dates

Filing dateJun 24, 2022
Grant dateOct 15, 2024
Priority date
Expiry dateDec 14, 2042

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH03K21/02
  • WIPO fieldBasic communication processes
  • WIPO sectorElectrical engineering

Abstract

An example apparatus includes multiplexer circuitry configured to couple a communication module to at least one of a data bus input or a test signal; and embedded pattern generator (EPG) circuitry coupled to the multiplexer circuitry, the EPG circuitry including: clock divider circuitry including a plurality of clock outputs, the clock divider circuitry configured to be coupled to an output of a clock, the plurality of clock outputs configured to be of a frequency equal to a division of a frequency of the output of the clock; a multiplexer including a multiplexer output, the multiplexer configured to couple one of the plurality of clock outputs to the multiplexer output; and signal generator circuitry including an input clock, an EPG input, and a plurality of data outputs, the input clock coupled to the multiplexer output, the signal generator circuitry configured to generate a data stream.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.