Ultra-low power instant lock phase lock loop (PLL)
US12119831B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2023 |
| Grant date | Oct 15, 2024 |
| Priority date | — |
| Expiry date | Feb 23, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods reduce a locking time of a type-II all-digital phase-locked loop (ADPLL) circuit by performing steps that comprise receiving a reference signal having a reference frequency and setting a digitally controlled oscillator (DCO) to a target frequency greater than the reference frequency. The DCO generates an output signal that is used to generate a feedback signal. A time-to-digital converter is used to determine an initial phase difference between the reference signal and the feedback signal, and a digital initial phase compensation circuit adjusts the initial phase difference to a substantially zero phase difference to reduce the locking time of the ADPLL circuit such that the ADPLL circuit reaches a steady-state condition in ten or fewer cycles of the reference signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.