Compensation method for overlay deviation
US12124175B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2021 |
| Grant date | Oct 22, 2024 |
| Priority date | — |
| Expiry date | Sep 22, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/20
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A compensation method for overlay deviation, including: obtaining x first inspection distribution maps; and performing a first iteration on wafers of an n-th lot according to the x first inspection distribution maps to obtain an n-th high-order overlay deviation model, that the wafers of the n-th lot include a plurality of n-th wafers, n is a natural number greater than or equal to one, and performing the first iteration includes: obtaining x n-th wafers to be inspected from the wafers of the n-th lot; allocating the x first inspection distribution maps, that each n-th wafer to be inspected corresponds to one first inspection distribution map; obtaining an n-th overlay accuracy information of each n-th wafer to be inspected according to a corresponding first inspection distribution map; and obtaining the n-th high-order overlay deviation model according to the x n-th overlay accuracy information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.