Fault detection during entry to or exit from low power mode
US12124309B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2022 |
| Grant date | Oct 22, 2024 |
| Priority date | — |
| Expiry date | Jan 13, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/034
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system-on-chip (SoC) having a switchable power domain capable of being placed in a standby mode during which a power supply of the switchable power domain is gated and having an always-on power domain. The always-on power domain includes an input sampling circuit, and the switchable power domain includes an input/output (IO) circuit configured to, during normal operation, receive data at a corresponding signal pin when an input buffer of the IO circuit is enabled, in which the corresponding signal pin is coupled to the input sampling circuit. The input sampling circuit is configured to, while the switchable power domain is entering the standby mode but before the power supply is gated, provide an override input enable signal to enable the input buffer of the IO circuit, sample an input bit value on the corresponding signal pin, and store the sampled bit value to provide an injection current fault indicator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.