Data processing system having a memory controller with inline error correction code (ECC) support
US12124328B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2022 |
| Grant date | Oct 22, 2024 |
| Priority date | — |
| Expiry date | Nov 12, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/805
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller includes a transaction scheduler circuit and a command queue. For each access request received by the memory controller, the transaction scheduler circuit is configured to allocate a new entry in a scheduler queue, store an access address corresponding to the access request as a data address into the new entry, generate an error correction code (ECC) address from the data address and store the ECC address into the new entry, and set a corresponding ECC mode field in the new entry to indicate whether the data address or ECC address of the new entry is to be exposed during arbitration. The transaction scheduler circuit, during an arbitration cycle, is configured to select a transaction from the scheduler queue using an exposed address of each valid entry, and is configured to provide the selected transaction to the command queue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.