Interface circuit and memory controller
US12124331B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 28, 2023 |
| Grant date | Oct 22, 2024 |
| Priority date | — |
| Expiry date | Jun 28, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0772
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interface circuit includes multiple signal processing devices and a monitor and calibration module. The monitor and calibration module includes multiple monitor circuits, multiple calibration circuits, a compensation accelerator and a processor. The monitor circuits monitor at least one of an amplitude, a frequency and jitter in at least one of a reception signal and a transmission signal to correspondingly generate a monitored result and monitor at least one of power supplying voltage and ground voltage to correspondingly generate a monitored result. The compensation accelerator collects the monitored results and generates a calibration control signal corresponding to each calibration circuit according to calibration commands. The processor generates the calibration commands based on the monitored results. The calibration circuits perform a corresponding calibration operation on the corresponding signal processing device in response to the calibration control signal to adjust a characteristic value of the signal processing device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.