Hardware translation request retry mechanism
US12124381B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 18, 2021 |
| Grant date | Oct 22, 2024 |
| Priority date | — |
| Expiry date | Nov 18, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system includes a hardware translation lookaside buffer (TLB) retry loop that retries virtual memory address to physical memory address translation requests from a software client independent of a command from the software client. In response to a retry response notification at the TLB, a controller of the TLB waits for a programmable delay period and then retries the request without involvement from the software client. After a retry results in a hit at the TLB, the controller notifies the software client of the hit. Alternatively, if a retry results in an error at the TLB, the controller notifies the software client of the error and the software client initiates error handling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.