Memory configuration within a data processing system
US12124720B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2022 |
| Grant date | Oct 22, 2024 |
| Priority date | — |
| Expiry date | Oct 13, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1446
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A System on Chip (SoC) includes a first core coupled to an interconnect; a second core coupled to the interconnect; a memory coupled to the interconnect and including a plurality of evenly sized partitions; and storage circuitry configured to store memory configuration information. The memory configuration information defines a memory configuration and is configured to indicate a series of swappable segments for each core of the SoC by indicating, for each core, a first number of partitions of the memory assigned to each of a first swappable segment and a second swappable segment for the core, the first swappable segment designated as an active segment and the second swappable segment designated as a first backup segment, and an enable indicator to indicate whether or not to assign the first number of partitions to a third swappable segment designated as a second backup segment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.