In-memory computing module and method, and in-memory computing network and construction method therefor
US12124736B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2021 |
| Grant date | Oct 22, 2024 |
| Priority date | — |
| Expiry date | Mar 31, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/54
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present application relates to an in-memory computing module and method, and an in-memory computing network and a construction method therefor. The in-memory computing module comprises at least two computing submodules, and low latency can be achieved when computing units in the computing submodules access memory units. Multiple computing submodules present a symmetric layer design, and such a symmetric layer structure facilitates the construction of a topology network so as to achieve large-scale or ultra-large-scale computation. The memory capacity of the memory units in each computing submodule can be customized, and designed flexibly. These computing submodules are in a bonding connection, and the data bit width after the bonding connection may be positive integer multiple of the data bit width of the computing units, so that high data bandwidth is achieved. The in-memory computing network uses the in-memory computing module, so that the requirements for different scales of computation can be satisfied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.