Digital signal processing device
US12124815B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 18, 2022 |
| Grant date | Oct 22, 2024 |
| Priority date | — |
| Expiry date | Jan 27, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/548
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital signal processor includes K first electronic circuits. The first inputs receive K groups of G successive coefficients of a polynomial. The polynomial are of degree N with N+1 coefficients, where K is a sub-multiple of N+1 greater than or equal to two and G is equal to (N+1)/K. The first electronic circuits are configured to simultaneously implement K respective Horner methods and deliver K output results. A second electronic circuit includes a first input configured to successively receive the output results of the first electronic circuits starting with the output result of the first electronic circuit having processed the highest rank coefficient of the coefficients. A second input is configured to receive a variable X and the second electronic circuit is configured to implement a Horner method and deliver a value of the polynomial for the variable X on the output of the second electronic circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.