Carry-lookahead adder, secure adder and method for performing carry-lookahead addition
US12124816B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2022 |
| Grant date | Oct 22, 2024 |
| Priority date | — |
| Expiry date | Apr 24, 2043 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A carry-lookahead adder is provided. A first mask unit performs first mask operation on first input data with the first mask value to obtain first masked data. A second mask unit performs second mask operation on second input data with the second mask value to obtain second masked data. A first XOR gate receives the first and second mask values to provide a variable value. A half adder receives the first and second masked data to generate a propagation value and an intermediate generation value. A third mask unit performs third mask operation on the propagation value with the third mask value to obtain the third masked data. A carry-lookahead generator provides the carry output and the carry value according to carry input, the generation value, and the propagation value. The second XOR gate receives the third masked data and the carry value to provide the sum output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.